Duolog Technologies , the award-winning developer of IP and SoC integration products, is presenting two papers at CDNLive! EMEA at the Dolce Hotel, Munich, from May 14th to 16th.
Duolog will be presenting as part of the Design & Verification Track on Wednesday May 16th at 11.30 am. This presentation will outline a methodology for formally defining IP programming sequences using a sequence definition language. Sequences leverage industry standard register management solutions to extend the HW/SW interface definition.
“Extending the HW/SW interface definition using formal programming sequences opens up exciting automation possibilities,” said David Murray, Duolog CTO and featured CDNLive speaker. “Sequences enable the auto-generation of documentation, verification test cases and software setup routines and deliver major improvements in HW/SW integration productivity.”
Duolog will also be presenting as part of the Functional Verification Track on Wednesday May 16th at 11.00 am. This presentation will describe how a System-Verilog based Universal Verification Methodology (UVM) test bench is used to verify a mixed-signal design. It is based on best practice experience gained by Duolog’s services team across a number of customer engagements.
“Mixed-signal verification flows are now reaching an inflection point at which traditional methodologies are no longer viable,” said Cesar Matias, Duolog’s Professional Services Manager. “Leveraging proven digital verification techniques to improve the verification of mixed-signal designs is therefore an increasingly attractive option.”
In addition to the presentations, Duolog is exhibiting at booth #9. The Duolog team will be demonstrating the industry-leading Socrates tool suite. Come see how to save time and effort by streamlining the IP/SoC integration and verification flow:
Rapid IP Integration using rules-based system assembly and connectivity
Comprehensive HW/SW integration solutions
F ormal IP/SoC programming sequence definition
