Non Members - 0.00
5-day custom training class made from two individual classes that Hardent offers.
System Verilog for Design (days 1-2)
The course is aimed at RTL designers who wish to learn about the new features of System Verilog for RTL design. Discussion will include constructs and features in System Verilog that are designed to capture design intent so that Simulation tools may analyse for correct RTL design practices and speed up the design process. While there are labs, Synthesis tools are not required.
System Verilog for Verification (days 3-5)
This course is aimed at verification engineers who are interested in applying the new verification features in System Verilog to their test benches. In addition to new datatypes and improvements to the Verilog syntax, System Verilog is an OOP (object Oriented Programming) language with exciting features like Constrained Randomization and Functional Coverage. The course stresses a methodology for implementing these features in your verification environment. The course is a consistent mix of lecture and lab exercises. Lab exercises are designed to reinforce the course material.
To book places, please contact Gerry.Byrne@edalics.com. This course is funded by Skillnets, through the Department of Education and Skills, and member company contributions.
