Non Members -
A detailed knowledge of how to build a class-based SystemVerilog verification environment is essential. For engineers with no class-based SystemVerilog knowledge or experience the Doulos Comprehensive SystemVerilog or SystemVerilog for Verification Specialists courses provide an appropriate preparation
Attendees will learn:
The principles of effective functional verification using UVM
The standard structure of UVM components and environments
How to use the UVM base class library in constructing your own verification environments
Making good use of UVM features for configuration, stimulus generation, reporting and diagnostics
How to build complete, powerful, reusable class-based UVM verification components and environments
Location: TBC
Fee: €1,500 per attendee
