Start date: 16 November 2021
Duration: 2.5 hour class, 2pm - 4:30pm, on 4 days, Tues. 16th to Fri. 19th Nov 2021
Location: Online course
Cost: Members €300 pp; Non-members €450 pp
Course code: N/A
This course provides 4 days of 2.5 hour lectures / day from Prof. Hanumolu focusing on high performance phase-locking techniques for clock generation, in which he is an accomplished researcher.
- Advanced phase-locking techniques for clock generation.
Who is the course for?
Experienced analog IC designers, who wish to deepen their knowledge about phase-locking and its applications to low-noise clock generation.
2.5 hour online class each day, 2pm to 4:30pm, on Monday to Friday, 16th to 19th Nov. 2021.
o Charge-pump PLLs
o Digital PLLs
o Hybrid PLLs
o Supply-regulated PLLs
o Multiplying delay-locked loops
o Injection-locked clock multipliers
Prof. Pavan Hanumolu (Fellow, IEEE) is a Professor with the Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Champaign, IL, USA. His research interests are in energy-efficient integrated circuit implementation of analog and digital signal processing, sensor interfaces, wireline communication systems, and power conversion. Prof. Hanumolu has served as a Technical Program Committee Member for the International Solid-State Circuits Conference, the Custom Integrated Circuits Conference, and the VLSI Circuits Symposium. He is the current Editor-in-Chief of the IEEE Journal of Solid-State Circuits.