Start date: 18 May 2020
Duration: 3 Days
Location: Online course, 11am - 6pm each day, max 12 participants
Cost: Members € 600; Non-members € 900
Course code: N/A
This 3-day Advanced RTL Design training class is intended for experienced digital IC designers. It will teach & demonstrate Advanced Design techniques mostly using Verilog while adding some new SystemVerilog features. Techniques used will emphasize efficient, synthesizable, RTL coding techniques.
Due to demand this course will be re-run on 26 - 28 May. It will delivered entirely online due to the COVID-19 virus. The course tutor, Cliff Cummings, is based in Utah, 7 hours behind Irish time, so the course will be held each day from 11am to 6pm.
- Advanced Design techniques
- Efficient, synthesizable, RTL coding techniques
Who is the course for?
Experienced digital IC designers.
3 days of advanced design theory and lab practicals, covering the following topics:
• Introduction & Overview of Verilog/SystemVerilog Design & Synthesis Resources SystemVerilog Enhancements & Methodology Overview
• Review of Important Verilog Coding Guidelines
• Latches & Priority Encoders
• Combinational Logic I
• Implicit .* and .name Port Instantiation
• Combinational Labs Review
• Combinational Logic II
• Sequential Logic
• Synchronous & Asynchronous Reset Design & DFT
• Design for Reuse / IP Design
• Finite State Machine (FSM) Design
• Multi-clock Clock Domain Crossing (CDC) & FIFO Design Techniques using SystemVerilog
Cliff Cummings has taught expert Verilog, SystemVerilog and OVM/UVM Verification to thousands of engineers world-wide since 1992 and has presented more than 50 papers on topics related to Verilog, SystemVerliog, synthesis and verification. More than 20 of Mr. Cummings’ works have been voted “Best Paper” at various conferences.
Mr. Cummings, was a member of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog Standards Groups from 1994 to 2012, and has received IEEE awards acknowledging his contributions towards developing these important IEEE and Accellera Verilog & SystemVerilog Standards.