Start date: 06 December 2021
Duration: 3 Days, times as per schedule below
Location: Remote Learning
Cost: Members € 500; Non-members € 750
Course code: N/A
This 3 day course is for Verification Engineers with experience using the Universal Verification Methodology (UVM) who wish to take their skills and knowledge of the library to the next level. Real world UVM testbenches have issues that require knowing how to apply the UVM library to solve them. Issues such as multiple interfaces to the DUT, concurrent process synchronization, interrupts and transaction responses. In this Advanced UVM class you will gain experience in dealing with these and other testbench challenges.
Due to demand, this course is being rerun on:
26 - 28 April, trainer Tim Corcoran
24 - 26 May, trainer Tim Corcoran
6 - 8 Dec, trainer Nigel Woolaway
The class works through various testbench issues and challenges, describing and recommending solutions. You will be able to apply these solutions to your testbench. You will also take away from this class detailed real world example testbenches that provide a great reference in doing your testbench.
Who is the course for?
UVM Verification engineers who want a deeper understanding of the library and the methodology. A knowledge of UVM and the SystemVerilog language, especially object oriented SV, is a prerequisite.
The presentation of the course takes place for about 4-5 hours each day. There are 3 labs included in this course and each lab is designed to complete in 45 minutes. The proposed class schedule is as follows:
Dec 6th: 9:15am-4:00pm Irish time
Dec 7th: 9:15am-3:00pm Irish time
Dec 8th: 9:15am-2:00pm Irish time
• DUT/TB Interface and Encapsulation
• Templates and Callbacks
• Advanced Factory Pattern
• Configuration and Polymorphism
• Virtual Interface Issues
• Virtual Sequences
Day 3 (Lots of topics, students will help select and prioritize)
• Response Handling
• Error Injection
• Reuse Issues
• Advanced RAL
• Interface Classes
• Command Line Processing
Nigel Woolaway is President and co-founder of Leading Edge based in Milan. Nigel initially worked as a designer on military and commercial communication systems and started developing verification methodologies for digital ASIC and full custom designs in 1983. He has since held various engineering and management roles in the field of design and verification at OEMs and EDA providers. Nigel has trained hundreds of engineers on three continents in the usage of VHDL, Verilog, SystemVerilog and UVM. In addition to training Nigel provides consulting services on UVM testbench development to companies in Europe and the Middle East.