Start date: 11 March 2025
Duration: 3 Days, 9:15am to approx. 4:00pm each day
Location: Online course
Certificate: N/A
Cost: Members € 500; Non-members € 750
Course code: N/A
Programme overview
This three day course is a mixture of lectures and subsequent lab exercises. Note that the course assumes that the students are already completely familiar with UVM and have significant practical experience in the creation of UVM testbenches. The purpose of the course is to examine established practices and introduce alternative methods which can be applied to overcome the challenges which often occur during the creation of complex testbenches. It will be delivered as an interactive remote learning course with a maximum of 12 participants to maintain high quality training.
Learning outcomes
Students leave this course with an enhanced set of tools and methodologies which can immediately be applied both to existing and new testbenches. The course materials include a selection of real-world testbenches incorporating the methodologies described. These can be used in whole or part during the creation of testbenches for customer designs.
Who is the course for?
This course is for experienced Verification Engineers, with about 2 years experience in verification, wishing to learn alternative techniques to resolve complex testbench challenges.
Schedule
The complete list of topics below would require 4 to 5 days to cover, so trainees will be polled as to which ones to include in a reduced 3-day schedule of the topics of most interest.
DUT-Testbench Interface and Configuration
Sharing Configuration Parameters
The Dual Top Simulation Approach
Efficient usage of UVM databases
Hierachical Configuration Objects
Hierarchical UVM Environments
Direct Method Calls
Sharing Configuration Parameters
The Dual Top Simulation Approach
Efficient usage of UVM databases
Hierachical Configuration Objects
Hierarchical UVM Environments
Direct Method Calls
Container Classes
The uvm_queue Class
The uvm_pool and uvm_object_string_pool Class
IEEE UVM Considerations
Building Reusable Code
The Template Method Pattern
The uvm_callback Class
Implementing Callbacks
Process Synchronisation
The uvm_event and uvm_event_pool Classes
The uvm_barrier and uvm_barrier_pool Classes
Implementing and Using Barriers
Phasing Techniques
Phase Callbacks and Applications
Phase awareness in non-components
Synchronising Common and UVM Domain Phases
Watchdogs
Phase Timeouts
The uvm_heartbeat Class
Using the Heartbeat Object
Message Catching
The uvm_report_catcher Class
Report Catcher API
Attaching the Report Catcher
UVM Factory – Beyond the Basics
The type-based and string-based Factories
The uvm_component_registry Class
Exploiting the string-based Factory
Configurability using Polymorphism
Polymorphism and the Testbench Components
Polymorphism and the Transaction Items
Polymorphism and the Sequences
System Configuration
Polymorphic Virtual Interfaces
Virtual Interface Wrapper Classes
Virtual Interface Proxy Classes
Connecting Polymorphic Interfaces to the Testbench
Hierarchical Sequences
Hierarchy Recommendations
Providing a Sequence API
Getting Sequencer Handles
Custom Response Handling
Handling Response Queue Overload
The response_handler Callback
Passing Responses to Calling Sequences
Interrupt Handling
Expected and Unexpected Interrupts
Interrupt Service Routines
Sequencer Locking and Grabbing
Reset Handling
Expected and Unexpected Resets
Using UVM Barriers for PoR
Register Model Reset Sequences
Error Injection
Transaction Layer Error Injection
Dynamic Link Layer Error Injection
The Error Injection Manager
Interface and Block Re-use
Reusing Agents
Reusing Environments
Chip Level Simulation Considerations
Advanced Register Access Layer Techniques
Memory Allocation Manager
Enabling Burst Register Access
Customising Registers Using Hooks and Callbacks
Interface Classes
Defining an API
Example Usage – Phase Awareness
Example Usage – Flag Wrapper
Command Line Processing
The uvm_cmdline_processor Class
Extracting Argument Values
Built-in Command Line Arguments
Alternatives To The Inheritance Pattern
Inheritance vs Composition
The Strategy Pattern
The Decorator Pattern
The Object Pool Pattern
Trainer Profile
Nigel Woolaway is President and co-founder of Leading Edge based in Milan. Nigel initially worked as a designer on military and commercial communication systems and started developing verification methodologies for digital ASIC and full custom designs in 1983. He has since held various engineering and management roles in the field of design and verification at OEMs and EDA providers. Nigel has trained over a thousand engineers on three continents in the usage of VHDL, Verilog, SystemVerilog and UVM. His ability to explain complex concepts in an easily understandable form enables his students to complete the Advanced UVM training with a clear understanding of UVM application to complex real-world testbenches. In addition to training Nigel provides consulting services on UVM testbench development to companies in Europe and the Middle East.
Tim Corcoran is the principal developer of all the SystemVerilog and UVM courses delivered by Leading Edge. Tim is a dynamic public speaker with decades of experience presenting complex, sometimes dry subject matter in a clear, understandable, engaging style. He has taught thousands of students all over the world. The courses he developed and teaches are derived from his 30+ years of experience in the EDA industry particularly in the areas of Software Modeling and Hardware Verification Methodologies. His excellent people skills and sense of humor have made Tim a highly successful partner for EDA vendor-partners and Design/Verification customers alike.
Email training@midasireland.ie for bookings and queries
