Start date: 16 January 2023
Duration: 5 Half Days, 9am - 1pm each day
Location: Online course
Cost: Members € 500; Non-members € 750
Course code: N/A
This 5 half-day introductory Digital Design Fundamentals course is a re-run of the course held twice in 2020 as an interactive remote learning course, with a maximum of 10 participants to maintain high quality training.
This course develops in each participant a "how to do" skill applied to Digital Design. This style uses a lecture/presentation based explanation followed by extensive use of hands-on design and coding practice. This method of teaching has been tried and honed over many years of teaching these topics.
Due to popularity, this course is being rerun online on 16 - 20 Jan and 3 - 7 Apr 2023 after being held twice in 2022: 11 - 15 Apr and 23 - 27 May and twice in 2021: 29Mar - 2Apr and 14 - 18 Jun 2021
On completion of the course, participants will be able to:
1. Design single and multiple FSM solutions to introductory digital design problems.
2. Use Top Down design methodologies for bigger design problems.
3. Describe and Use a digital design flow i.e. Design, Code, Synthesis with Constraints, place and route and download to FPGA (using Vivado)
4. Write efficient Verilog/SystemVerilog RTL models for synthesis and Simulation.
5. Design and write self checking simulation testbenches.
6. Be able to consider various coding styles for combinational and synchronous logic.
7. Understand multi-clock system design issues.
8. Understand AMBA bus protocols and design to a chosen AMBA Bus standard.
9. Be aware of verification methodologies based on SystemVerilog.
Who is the course for?
This introductory digital design course is designed to upskill graduate engineers or more experienced engineers working in other areas to design and code appropriate digital systems to a professional standard.
Presentation 1: State of the art in Digital Design Technology, CPU, SOC, ASIC, FPGA, Memory. Overview of Digital Systems Design, Flow and Tools.
Review of Digital Logic Basic Elements – Logic Gates, Multiplexor, Flip-Flop. Use of Timing Diagrams to test behaviour of logic circuits.
Introduction to Basic Verilog Modelling of combinational logic and synchronous logic. Different coding methods. Coding of a basic functional testbench. Correct Application of stimulus to UUT.
Workshop 1: Instructor Led, Verilog Coding of a logic schematic with switches and LEDs. Writing verilog self-checking testbench to test schematic.
Presentation 2: Introduction to Finite State Machines (FSMs). Logic derivation from FSMs. Application of FSMs to design solutions to various problems e.g. simple Receive UART.
Verilog Coding of FSMs – different styles of coding.
Workshop 2: Participant Led, Design an FSM to solve simple problem e.g. Transmit UART. Coding and self-checking testbench to test this design.
Presentation 3: Top Down Design: Design of 16×8 FIFO from Flips-Flops
Workshop 3: Code and test of 16×8 FIFO.
Presentation 4: ARM and AMBA, APB, AHBLite and AXI4 buses, how they work and
compare. Design AMBA bus DMA controller using one of the AMBA protocols.
Workshop 4: Code and Test of AHB DMA Controller. More complex testbench.
Presentation 5: Timing Analysis(STA) of digital blocks.
Single bit Asynchronous Inputs to FSMs and synchronization methods. Design Method to safely facilitate bus crossing asynchronous interface – method 1.
Workshop 5: Design of memory controller for simple asynchronous SRAM.
Code and test this design including bus functional model (BFM) of the SRAM.
Presentation 6: Design of a simple Microprocessor
Wrap up: Summary of Course and Participant Survey and Feedback.
Richard Gahan has over 20 years experience delivering modules in digital design, Microprocessor Architecture Design,Verilog and scripting languages to industry in Ireland and to about 1,000 Irish undergraduates and post graduates in TUDublin as well as to over 1,600 students at NJTech University, Nanjing, China. Richard has also consulted in digital design projects to industry in Ireland over many years.