Start date: 22 September 2022
Duration: 12 Weeks, 22 Sept - 15 Dec
Location: Online course, Thursdays 4pm to 7pm for 12 weeks
Certificate: 10 ECTS
Cost: Members € 950; Non-members € 1,425
Course code: N/A
This 12 week CPD module was originally run in Sept-Dec 2020. It was rerun in Sep-Dec 2021and will be held again in Sept-Dec 2022. It will allow graduate engineers and engineers employed in other disciplines within the microelectronic sector to upskill such that they can become contributing digital designers within a team environment from day 1. The average participant workload on this CPD module will be 11 hours per week. The lectures and tutorials will be recorded and put online.
On completion of the module, participants will be able to:
A) Design single and multiple Finite State Machine(FSM) solutions to intermediate level digital design problems.
B) Use Top Down design methodologies to solve more complex digital design problems.
C) Write efficient Verilog RTL models for synthesis and simulation.
D) Design and write self-checking simulation testbenches
Who is the course for?
Novice FPGA/ASIC design engineers who may not have used verilog or a simulator before, this includes graduate engineers and engineers employed in other disciplines within the microelectronic sector to upskill such that they can become contributing digital designers within a team environment.
To apply for this level 9 module applicants will normally hold a 4-year degree in electronic engineering or cognate discipline. However, prior suitable industry experience may be taken into account.
12 week semester on the topics below (click on “Full course details” above to download course outline in detail):
Introduction to Basic Verilog Modelling of combinational logic and synchronous logic.
Different coding methods.
Verilog Coding of FSMs – different styles of coding.
Coding of a basic functional testbench. Correct Application of stimulus to UUT.
Self-Checking testbench. Building up testbench complexity.
Test Specifications. Unit testing and system testing. Use of Linting.
Testing Silicon – Functional testing, BIST, SCAN and production testing.
Description of Verification Methodologies – UVM. Verilog and UPF in verification.
Introduction to Finite State Machines (FSMs). Logic derivation from FSMs.
Application of FSMs to design solutions to various problems e.g. simple UART receive and transmit, Sequence Detect, Memory Controller, Memory Arbitration.
Introduction to Top Down Design Methodology and application to Design of 16×8 FIFO from Flips-Flops or similar.
ARM and AMBA, APB, AHBLite and AXI4 buses, how they work and compare.
Design of AMBA bus DMA controller using one of the AMBA protocols.
Timing Analysis (STA) of digital blocks. Minimum and maximum time calculations. Chip I/O timing and PLL application.
Single bit Asynchronous Inputs to FSMs and synchronization methods.
Metastability and Reliability of single bit and double synchronisation methods.
Design Method to safely facilitate bus crossing asynchronous interface — method 1.
Efficient Data Bus Crossing of asynchronous interfaces using FIFO.
Design of a simple Microprocessor or similar project.
FPGAs – Overview of the architecture and building blocks of XILINX, Altera (Intel)
and Microsemi FPGAs.
Comparison of FPGA to ASIC development. IO Standards, DDR Memory and DDR interfacing.
Richard Gahan is currently a Lecturer in Digital Design at TU Dublin, where he leads the MEng in Electronic Systems Design which has a major component in digital design and architecture. Previously Richard has held a number of positions in industry as Design Engineer, Project Leader, Design Architect, Design Centre Manager and Consultant Engineer.
Richard holds 12 patents is different areas of digital design, and has published research papers in areas of digital design and efficient video processing. Richard has taught courses in digital design to thousands of students and industry courses over several years.