Learning outcomes

On completion of the module, participants will be able to:
A) Design single and multiple Finite State Machine(FSM) solutions to intermediate level digital design problems.
B) Use Top Down design methodologies to solve more complex digital design problems.
C) Write efficient Verilog RTL models for synthesis and simulation.
D) Design and write self-checking simulation testbenches

Who is the course for?

Schedule

12 week semester on the topics below (click on “Full course details” above to download course outline in detail):

Introduction to Basic Verilog Modelling of combinational logic and synchronous logic.
Different coding methods.

Verilog Coding of FSMs – different styles of coding.

Coding of a basic functional testbench. Correct Application of stimulus to UUT.
Self-Checking testbench. Building up testbench complexity.

Test Specifications. Unit testing and system testing. Use of Linting.
Testing Silicon – Functional testing, BIST, SCAN and production testing.
Description of Verification Methodologies – UVM. Verilog and UPF in verification.

Introduction to Finite State Machines (FSMs). Logic derivation from FSMs.
Application of FSMs to design solutions to various problems e.g. simple UART receive and transmit, Sequence Detect, Memory Controller, Memory Arbitration.

Introduction to Top Down Design Methodology and application to Design of 16×8 FIFO from Flips-Flops or similar.

ARM and AMBA, APB, AHBLite and AXI4 buses, how they work and compare.
Design of AMBA bus DMA controller using one of the AMBA protocols.

Timing Analysis (STA) of digital blocks. Minimum and maximum time calculations. Chip I/O timing and PLL application.

Single bit Asynchronous Inputs to FSMs and synchronization methods.
Metastability and Reliability of single bit and double synchronisation methods.
Design Method to safely facilitate bus crossing asynchronous interface — method 1.

Efficient Data Bus Crossing of asynchronous interfaces using FIFO.

Design of a simple Microprocessor or similar project.

FPGAs – Overview of the architecture and building blocks of XILINX, Altera (Intel)
and Microsemi FPGAs.
Comparison of FPGA to ASIC development. IO Standards, DDR Memory and DDR interfacing.

To download the detailed course schedule including assignments (the 6th assignment is an elective choice between options a and b), please click on the “Full Course Details” button on the image above.

Trainer Profile

Richard Gahan is currently a Lecturer in Digital Design at TU Dublin, where he leads the MEng in Electronic Systems Design which has a major component in digital design and architecture. Previously Richard has held a number of positions in industry as Design Engineer, Project Leader, Design Architect, Design Centre Manager and Consultant Engineer.

Richard holds 12 patents is different areas of digital design, and has published research papers in areas of digital design and efficient video processing. Richard has taught courses in digital design to thousands of students and industry courses over several years.