Start date: 13 September 2022
Duration: 15 Weeks, 12 x 3 hour classes + self-directed learning hours
Location: Online course, Tuesdays 4pm to 7pm for 12 weeks
Certificate: Level-9 Special Purpose Award (10 ECTS Credits)
Cost: Members € 950; Non-members € 1,425
Course code: N/A
This course is designed to give the learner a thorough grounding in digital ASIC verification methodologies. It explores topics such as what is verification, why we do it and how we do it. The course is not a SystemVerilog nor a UVM course. Instead it is a wide ranging course covering topics such as verification philosophy and approach, verification planning, testbench design and architecture, verification domains and strategies, metrics and coverage. Different levels and types of verification are explored (e.g. functional, power-aware, gate level simulation, mixed signal, emulation etc.). To promote deeper learning, students will be exposed to regular practical exercises on key aspects of verification through labs and mini-assignments. It is recommended that participants allow for a time commitment in the region of 6 to 9 hours per week for course attendance, self-directed learning hours and assignments.
On completion, participants will be able to:
• Analyse appropriate verification approaches for a given design from a wide range of verification techniques and methodologies.
• Write verification plans for sample systems/subsystems.
• Architect and design test benches and tests to facilitate reuse.
• Apply a range of verification techniques to a range of design types.
• Model systems and write drivers/monitors at different levels of abstraction.
• Interpret coverage metrics and requirements tracking to determine verification closure.
Who is the course for?
The course is primarily aimed at engineers who are about to or have recently taken up roles in verification teams. This may include recent graduates or engineers moving from other roles into verification roles. Applicants should have some knowledge of SystemVerilog.
To apply for this level 9 module, applicants will normally hold a 4-year degree in electronic engineering or cognate discipline. However, prior suitable industry experience may be taken into account.
Verification Overview and Philosophy
What is verification and why do we do it? Levels of verification (unit, IP, subsystem, system)/ Types of verification (Functional, PA, GLS, CDC, MSV, FW, Emulation) etc./ Typical bugs /Types of tests (register testing, directed, constrained random, stress testing, performance) / Compliance testing (protocols and industry standards)
Inputs to verification planning: specifications, requirements, industry standards, company guidelines, legacy product specifications / verification strategies and methodologies (simulation, formal verification, emulation, modelling)
Re-use/maintainability / documentation / revision control / synthesizable testbenches
drivers, monitors, checkers / models / reference files / levels of abstraction (TLM etc.) /object-oriented environments.
Verification Domains & Strategies
Functional / power-aware / gate level simulation / formal / mixed-signal / co-simulation (note: co-simulation and mixed signal covered only at an awareness level).
Metrics & Coverage
Code Coverage/ Functional Coverage / Requirements Coverage and Tracking/ Testbench Coverage / Metric Trends & Analysis.
Peter Gorman is currently a lecturer in TUS, Limerick (formerly Limerick IT). Following a career of approximately 20 years in the FPGA and ASIC design industries with a range of high profile multinational companies, Peter joined TUS in 2009 and since then has alternated his time between industry and academia. During his time in industry, Peter co-authored The ASIC Handbook which was published by Prentice-Hall in 2002.
Since joining TUS, Peter has developed and delivered modules in Digital Signal Processing, Engineering Maths, IP-Networking, Digital Electronics, Digital Video and Technical Communications. Industry-based areas of expertise include digital video, USB and KVM technologies.