Start date: 10 September 2024
Duration: 15 weeks (12 Lectures, Tuesdays 4-7pm over 15 week period, plus additional self-directed learning hours)
Location: Online course
Certificate: Level-9 Special Purpose Award (10 ECTS Credits)
Cost: Members € 950; Non-members € 1,425
Course code: N/A
Programme overview
This course is designed to give the learner a thorough grounding in digital ASIC verification methodologies. It explores topics such as what is verification, why we do it and how we do it. The course is not a SystemVerilog nor a UVM course. Instead it is a wide ranging course covering topics such as verification philosophy and approach, verification planning, testbench design and architecture, verification domains and strategies, metrics and coverage. Different levels and types of verification are explored (e.g. functional, power-aware, gate level simulation, formal, emulation etc.). To promote deeper learning, students will be exposed to regular practical exercises on key aspects of verification through labs and mini-assignments. It is recommended that participants allow for a time commitment in the region of 6 to 10 hours per week for course attendance, self-directed learning hours and assignments.
This course was initially run in Sept-Dec 2023 and is being rerun in Sept-Dec 2024 to meet demand.
Learning outcomes
On completion, participants will be able to:
• Create verification plans for sample systems/subsystems.
• Architect and design test benches and tests to facilitate reuse.
• Apply a range of verification techniques to a range of design types.
• Write models and write drivers/monitors at different levels of abstraction.
• Interpret coverage metrics and requirements tracking to determine verification closure.
Who is the course for?
This course is primarily aimed at engineers who are about to or have recently taken up roles in verification teams. This may include recent graduates or engineers moving from other roles into verification roles. This is not an advanced verification course. It is therefore probably not suited to experienced verification engineers. Applicants should have some knowledge of SystemVerilog and using Linux as an OS. Some basic prior knowledge of UVM would be helpful but is not a requirement.
To apply for this level 9 module, applicants will normally hold a 4-year degree in electronic engineering or cognate discipline. However, prior suitable industry experience may be taken into account.
Course Outline
Verification Overview and Philosophy
What is verification and why do we do it? Levels of verification (unit, IP, subsystem, system)/ Types of verification (Functional, PA, GLS, CDC, MSV, FV, Emulation) etc./ Typical bugs /Types of tests (register testing, directed, constrained random, stress testing, performance) / Compliance testing (protocols and industry standards)
Verification Planning
Inputs to verification planning: specifications, requirements, industry standards, company guidelines, legacy product specifications / verification strategies and methodologies (simulation, formal verification, emulation, modelling)
Testbench Design/Architecture/Implementation
Re-use/maintainability / documentation / revision control / synthesizable testbenches
drivers, monitors, checkers / models / reference files / levels of abstraction (TLM etc.) /object-oriented environments.
Verification Domains & Strategies
Functional / power-aware / gate level simulation / formal / mixed-signal / co-simulation (note: co-simulation and mixed signal covered only at an awareness level).
Metrics & Coverage
Code Coverage/ Functional Coverage / Requirements Coverage and Tracking/ Testbench Coverage / Metric Trends & Analysis.
Indicative Assignments
Students will have to complete a series of mini-assignments and shorter practical labs. These will cover areas such as:
– designing a complete systemVerilog testbench to test a sample DUT
– designing a complete UVM testbench to test a sample DUT
– code coverage
– implementing a set of SVA testbench specifications
– verification management and tracking
– research report and presentation on ‘The State of the art in Digital Verification’
** The above assignment and content lists are indicative and may vary slightly depending on group dynamics and available time.
Trainer Profile
Peter Gorman is currently a lecturer in TUS, Limerick. Following a career of approximately 20 years in the FPGA and ASIC design industries with a range of high profile multinational companies, Peter joined TUS in 2009 and since then has alternated his time between industry and academia. During his time in industry, Peter co-authored The ASIC Handbook which was published by Prentice-Hall in 2002.
Since joining TUS, Peter has developed and delivered modules in Digital Signal Processing, Engineering Maths, IP-Networking, Digital Electronics, Digital Video and Technical Communications. Industry-based areas of expertise include IP-Networking, digital video, USB and KVM technologies.
Email training@midasireland.ie for bookings and queries
