Start date: 10 December 2019
Duration: 2 Days
Location: Analog Devices, Raheen Business Park, Limerick
Cost: Members € 400, Non-Members €600
Course code: N/A
This 2-day course teaches Essential Digital Design Techniques. Delegates require no prior involvement in digital design projects or HDL knowledge, but should be familiar with the basic principles of digital electronics.
Learn fundamental Digital Design Techniques and reinforce that theory with lab practicals
Who is the course for?
Design, Application or Test Engineers wishing to learn fundamental Digital Design Techniques.
2 days of Digital Design Techniques and lab practicals, covering the following topics:
Designing with programmable logic and ASICs • Synchronous design techniques • Using HDLs
Digital Design Fundamentals
Representing bits and three-states • Unsigned and signed (two’s complement) numbers • Static and dynamic definition of combinational logic • Logic minimisation • Avoiding asynchronous sequential logic
Synchronous Sequential Logic
Principles • Using D-type flip-flops • Characterisation – timing constraints • Timing violations and metastability issues • Timing performance of synchronous systems • Static timing analysis • Other flip-flop types
An Overview of HDL-Based Design
First and second generation HDLs • VHDL and Verilog • Design process using HDLs
Introduction to Programmable Logic
Survey of programmable logic devices •: Selecting an appropriate device • Importance of the internal structure • I/O pin standards • Pull-ups; open collector; tristates and bi-directional tristate bubble-up • Pin assignment • JTAG boundary scan
Common Functions and their Implementation
Encoders and decoders • Priority encoders • Multiplexers • Tristates used as Muxes • Parity generator • Shift Registers • Johnson (ring) “counters” • Linear Feedback Shift Registers
Half and full adders • Large adders •: Carry lookahead adder • Pipelining • Synthesis of adders • Counters • Wide counters • Binary to BCD conversion • Serial arithmetic • Importance of synchronous design
Synchronous Finite State Machines and Memories
Definition • Graphical entry and symbolism • Moore and Mealy structures • Implementation • State encoding and optimisation • Using HDLs to design FSMs • Using memories • Memory types
Introduction to ASICs
ASIC types and technologies • ASIC economics • Design for test • Design process for ASICs
Matthew Taylor has been a member of the Doulos team since 2014, where he teaches classes in VHDL, Verilog, SystemVerilog and UVM.
Prior to joining Doulos he was at Sony for 16 years where he was involved in the project management and design of ICs for digital TV and mobile phones. He was a key member of the team that set up Sony’s Nagare design flow and led the team that set up their transaction-level, reusable verification environment.
Prior to Sony he was at Siemens for 8 years where he designed FPGAs and ICs for radio applications..