Start date: 21 August 2023
Duration: 9am - 1pm for 4 days
Location: Online course
Certificate: Credly Online certificate
Cost: Members € 1300; Non-members € 1,950
Course code: N/A
IC Mask Design’s FinFET Layout course takes an in-depth look at the key challenges involved in the layout of high precision and high-speed Analog designs on 16nm technology nodes and below.
Learn the key fundamentals in FinFET Layout
Learn how to transition effectively from a planar background to FinFET nodes
Who is the course for?
This course is designed for Layout Engineers and Design Engineers doing layout and/or design on FinFET technology nodes, or for anyone transitioning to smaller FinFET technology nodes.
FinFET – Layout and key considerations (structure, fins, alignment & orientation).
Local interconnect strategies and challenges (cut layers, IR drop, EM).
Electromigration and IR strategies.
Metal colouring schemes.
Implementing WSP’s (design grids).
Lithography – layout methodologies for improving the lithography and etch process.
Intro and use of tuck poly.
Poly in traditional diffusion only structures.
Cut layers – ideal use scenarios and avoidance.
LDE at FinFET; what has changed and what is new.
Designing out density issues layout from both a manufacturing perspective and a design perspective.
Continuous diffusion strategies – challenges, risks, and solutions.
Device matching at FinFET nodes.
Recognising latch-up risk and improving immunity.
Transitioning from traditional substrate noise isolation schemes.
Ciaran Whyte is one of the founding members of IC Mask Design, as Chief Technical Officer he is responsible for all technical activity and the development and administration of all training courses. Ciaran has been training Layout Engineers for over 25 years and has completed Layout training with over 4000 engineers to date.