SystemVerilog for Verification

Start date: 18 October 2021

Duration: 4 Days, 9:15 am to approx. 4:00 pm each day

Location: Online course

Certificate: N/A

Cost: Members € 600; Non-members € 900

Course code: N/A

Programme overview

This 4-day course is an introduction to the SystemVerilog language, focusing on verification of digital RTL designs. The ideal attendee is a verification engineer who has experience with the Verilog language and wants to deploy a modern object oriented approach. It is delivered as an interactive remote learning course with a maximum of 12 participants to maintain high quality training.
Note: The dates for this course have been changed to 18 - 21 Oct from 29 Nov - 2 Dec to suit attendees better, so the following are the dates for reruns of the course in 2021:
8th - 11th Mar, trainer Tim Corcoran
10th - 13th May, trainer Tim Corcoran
18 - 21 Oct (instead of 29th Nov - 2nd Dec), trainer Nigel Woolaway

Learning outcomes

Participants will be able to develop object oriented SystemVerilog test benches to verify digital RTL designs. This course is also an ideal precursor to studying the Universal Verification Methodology (UVM).

Who is the course for?

Digital RTL verification engineers. A knowledge of the Verilog language is a prerequisite.


Day 1
Advanced Testbenches
Extensions to Verilog: Abstract Arrays, Aggregation, Packages
Tasks & Function Enhancements
Synchronization & Concurrency: Fork-join variations, Mailboxes & Semaphores
Day 2
Intro to OOP
Handles, Objects, Constructors
Virtual Interfaces
Virtual methods
Advanced Concepts:
Abstract Classes
Day 3
Constrained Randomization:
Stimulus Generation
Constraint blocks
randomize() method
Control-path randomization
Stimulus scenarios
Functional Coverage:
Cross Coverage methods & options
Day 4
Immediate & Concurrent
Sequences & Properties:
Blocks, Operators
Methods & Arguments
Local variables
Using Assertions:
Directives (assert & cover)
Multi-clock Assertions

Trainer Profile

Nigel Woolaway is President and co-founder of Leading Edge based in Milan. Nigel initially worked as a designer on military and commercial communication systems and started developing verification methodologies for digital ASIC and full custom designs in 1983. He has since held various engineering and management roles in the field of design and verification at OEMs and EDA providers. Nigel has trained hundreds of engineers on three continents in the usage of VHDL, Verilog, SystemVerilog and UVM. In addition to training Nigel provides consulting services on UVM testbench development to companies in Europe and the Middle East.

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