Start date: 23 October 2023
Duration: 4 Days, 9:15 am to approx. 4:00 pm each day
Location: Online course
Certificate: N/A
Cost: Members € 650; Non-members € 975
Course code: N/A
Programme overview
This 4-day course is an introduction to the SystemVerilog language, focusing on verification of digital RTL designs. The ideal attendee is a verification engineer who has experience with the Verilog language and wants to deploy a modern object oriented approach. It is delivered as an interactive remote learning course with a maximum of 12 participants to maintain high quality training.
The next rerun of this popular course has been scheduled for: 23 - 26 Oct after a rerun on 21 - 24 Feb 2023 and 4 successful reruns in 2022: 7 - 10 Feb, 7 - 10 Mar, 28 - 31 Mar and 30 Aug - 2 Sept. 2022 and 3 reruns in 2021: 8th - 11th Mar, 10th - 13th May and 18 - 21 Oct.
Learning outcomes
Participants will be able to develop object oriented SystemVerilog test benches to verify digital RTL designs. This course is also an ideal precursor to studying the Universal Verification Methodology (UVM).
Who is the course for?
Digital RTL verification engineers. A knowledge of the Verilog language is a prerequisite.
Schedule
Day 1
Advanced Testbenches
Extensions to Verilog: Abstract Arrays, Aggregation, Packages
Tasks & Function Enhancements
Interfaces
Synchronization & Concurrency: Fork-join variations, Mailboxes & Semaphores
Day 2
Classes:
Intro to OOP
Handles, Objects, Constructors
Virtual Interfaces
Inheritance
Virtual methods
Hiding
Advanced Concepts:
Parameterization
Polymorphism
Abstract Classes
Day 3
Constrained Randomization:
Stimulus Generation
Constraint blocks
randomize() method
Control-path randomization
Stimulus scenarios
Functional Coverage:
Covergroups
Coverpoints
Cross Coverage methods & options
Day 4
Assertions:
Immediate & Concurrent
Sequences & Properties:
Blocks, Operators
Methods & Arguments
Local variables
Using Assertions:
Directives (assert & cover)
Bind
Multi-clock Assertions
Trainer Profile
Nigel Woolaway is President and co-founder of Leading Edge based in Milan. Nigel initially worked as a designer on military and commercial communication systems and started developing verification methodologies for digital ASIC and full custom designs in 1983. He has since held various engineering and management roles in the field of design and verification at OEMs and EDA providers. Nigel has trained hundreds of engineers on three continents in the usage of VHDL, Verilog, SystemVerilog and UVM. In addition to training Nigel provides consulting services on UVM testbench development to companies in Europe and the Middle East.
Please email training@midasireland.ie for further queries or to book places
