Start date: 18 October 2022
Duration: 4 Days
Location: Online course, 11am - 6pm each day
Cost: Members € 600; Non-members € 900
Course code: N/A
This 4-day Universal Verification Methodology training class teaches important UVM Verification techniques. About 30% if this course is comprised of labs to practice the theory so as to better retain the UVM concepts explained in the course. It will be delivered entirely online due to the COVID-19 virus. The course tutor, Cliff Cummings, is based in Utah, 7 hours behind Irish time, so the course will be held each day from 11am to 6pm.
In order to meet demand reruns of this course are scheduled for 21 - 24 Feb and 22 - 25 Mar and 10 - 13 May 2022 and 18 - 21 Oct 2022.
Learn the theory of Universal Verification Methodology and reinforce that theory with lab practicals. Understand why UVM works the way it does in a fast paced course, which includes 10 full self-checking labs among the 13 labs included in the course.
Who is the course for?
Engineers wishing to learn how to apply UVM for verification of digital IC designs. If you are new to UVM or have less than 2 years of UVM experience with no formal UVM training, this is the course you should take. This UVM verification course assumes engineers already have a good working knowledge of both Verilog & SystemVerilog.
4 days of UVM Verification theory and lab practicals, covering the following topics:
• UVM Resources & Introduction
• Classes & Class Variables
• UVM Overview First Pass & uvmtb_template files
• Virtual Classes, Virtual Methods and Virtual Interfaces
• Introduction to Constrained Random Testing
• Introduction to Functional Coverage
• UVM Base Classes & Reporting (UVM print/display commands)
• UVM Transaction Base Classes, Sequences & Tests
• Top Module, DUT and Config Storage Techniques
• UVM Testbench Environment / Agent / Sequencer / Driver / Monitor
• UVM Scoreboards – Part I
• UVM Scoreboards – Part II
• Fork-Join Enhancements & Advanced UVM Sequence Generation
• Clocking Blocks and Verification Timing
• Transaction Level Modeling (TLM) Basics
• UVM Factory & Constructors
• Constrained Random Testing and Functional Coverage Part II
• UVM Register Abstraction Layer (RAL)
A detailed course syllabus in PDF format can download by clicking on the “Full Course Details” link in the image above.
Cliff Cummings has taught expert Verilog, SystemVerilog and OVM/UVM Verification to thousands of engineers world-wide since 1992 and has presented more than 50 papers on topics related to Verilog, SystemVerliog, synthesis and verification. More than 25 of Mr. Cummings’ works have been voted “Best Paper” at various conferences.
Mr. Cummings, was a member of the IEEE 1364 Verilog and IEEE 1800 SystemVerilog Standards Groups from 1994 to 2012, and has received IEEE awards acknowledging his contributions towards developing these important IEEE and Accellera Verilog & SystemVerilog Standards.