Complete Verilog

Start date: 28 September 2020

Duration: 5 Days, 6 hours per day

Location: Online course, max 12 participants

Certificate: N/A

Cost: Members € 600, Non-Members €900

Course code: N/A

Programme overview

Complete Verilog is a 5-day @ 6 hours / day online training course teaching the application of the Verilog® Hardware Description Language for FPGA and ASIC design. The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools in the FPGA or ASIC design flows.

Learning outcomes

You will learn how to use Verilog to design ASICs or FPGAs, write testbenches and behavioural models. Workshops comprise approximately 50% of class time and are based around carefully designed exercises to reinforce and challenge the extent of learning.

Who is the course for?

FPGA/ASIC/IC design, verification, layout or application engineers who about to embark on their first Verilog project or who have already acquired some practical experience in the use of Verilog, but wish to consolidate and extend their knowledge within a formal training environment.  Delegates should have a good working knowledge of digital hardware design.

Schedule

Introduction to Verilog
What is Verilog? • Scope of Verilog • Design flow for ASICs, CPLDs and FPGAs • Introduction to synthesis • Synchronous design • Timing constraints • Verilog books and internet resources

Modules
Modules & ports • Continuous assignments • Wire assignments • Comments • Names • Nets and strengths • Design hierarchy • Module instances • Primitive instances • Text fixtures • $monitor • Initial blocks • Variables

Nets and Values
Primitives • Wire assignments • Net types • Drive strengths • Logic values • Vectors • Numbers • Truncation • Signed numbers

Formatting, Timescale and Always
Output formatting • Timescales • Always blocks • $stop and $finish • Using wires and registers correctly

Always Blocks
RTL always blocks • Event control • Combinational logic sensitivity • If statements • Begin-end • Incomplete assignment and latches • FPGAs and latches • Unknown and don’t care • Conditional operator • Tristates

Procedural Statements
Case • casez • casex • full_case • parellel_case • For, repeat, while and forever loops • integers • Self-disabling blocks • Combinational logic synthesis

Clocks and Flipflops
Synthesising flip-flops & latches • Avoiding simulation race hazards • Nonblocking assignments • Asynchronous & synchronous resets • Clock enables • Synthesizable always templates • RTL synthesis technology • Inferring flip-flops • Making best use of RTL synthesis

Operators and Parameters
Bitwise, reduction, logical and equality operators • Part selects • Concatenation & replication • Shift registers • Conditional compilation • include • Parameters • localparam • Hierarchical names

FSM Synthesis
State transition diagrams • State machine architectures • FSM timing • Coding FSMs in Verilog • State encoding • One-hot state machines • Unreachable states & safe design practices

Arithmetic and Synthesis
Arithmetic operators and their synthesis • Vector arithmetic • Bit-length of expressions • Signed and unsigned values • Adder architectures • WYSIWYG arithmetic synthesis • Arithmetic optimization • Resource sharing

Tasks, Functions and Memories
Tasks • Task argument passing • Static vs automatic storage • Synthesis of tasks • Functions • Verilog memories • RAM modelling and synthesis • Inference vs instantiation • $readmemb and $readmemh • generate for/if/case •

File I/O
Writing to files • $display • $strobe • $write • $monitor • Opening a closing files • File descriptors • Reading from files • $fscanf • Raw file I/O • $fgets • $fgetc • $fseek • $ftell

Functional Simulation
Design flow through to P&R • Gate-level simulation • Back annotation using SDF.• PLD and ASIC design flow • Verilog libraries • Command-line options • Test benches • Comparing actual vs expected outputs • Behavioural modelling

Behavioural Verilog
Algorithmic coding • real • event control • wait • Named events • Fork & join • External disable • Intra-assignment timing controls • Overcoming clock skew • Continuous procedural assignment • defparam • Hierarchical names

Specialised Topics
Structural Verilog • Using built-in primitives • Gate, net & path delays • Specify blocks • State-dependent delays • Pulse rejection • Cell library modelling • library • liblist • config • The Verilog PLI • PLI applications • PLI routines • The PLI in practice • The VPI

SystemVerilog
Overview of SystemVerilog • Status of SystemVerilog • RTL enhancements • Interfaces • Assertions • Testbenches • C interface

Trainer Profile

Matthew Taylor has been a senior member of technical staff providing training courses since 2014. He teaches classes in VHDL, Verilog, SystemVerilog and UVM.
Prior to that, Matthew was at Sony for 16 years where he was involved in the design and verification of ICs for digital TV and mobile phones.
Prior to Sony he was at Siemens for 8 years where he designed FPGAs and ICs for radio applications. Matthew graduated from the University of Bath with a first-class degree in Electronics and Electrical Engineering and also has an MEng in Engineering.

Contact Gerry Byrne at Gerry.Byrne@midasireland.ie for full details