Start date: 04 January 2021
Duration: 2 hour class, 2pm - 4pm, on 5 days, Monday 4th to Friday 8th Jan 2021
Location: Online course
Cost: Members €250 pp; Non-members €375 pp
Course code: N/A
This course provides 5 days of 2 hour lectures / day from Prof. Hanumolu focusing on Clocking in Wireline SERDES Transceivers design, in which he is an accomplished researcher. It is the second SERDES design course following the Signaling course in December.
- Latest clocking techniques in high speed serial interface design
Who is the course for?
Experienced analog IC designers, who wish to deepen their knowledge about signaling in high speed serial interface design and learn from a world class expert on this topic.
2 hour online class each day, 2pm to 4pm, on Monday to Friday 4th to 8th Jan 2021. This is Part II of a two course series on this topic focused on Clocking (Part I focused on Signaling is being held in December):
1. Fundamentals of phase-locked loops (PLLs)
2. Advanced PLL architectures
3. Fractional-N PLLs
Clock & data recovery
1. CDR fundamentals
2. Phase/frequency detectors
3. D/PLL-based CDRs
4. Baud-rate CDRs
Prof. Pavan Hanumolu (Member, IEEE) is a Professor with the Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Champaign, IL, USA. His research interests are in energy-efficient integrated circuit implementation of analog and digital signal processing, sensor interfaces, wireline communication systems, and power conversion. Prof. Hanumolu has served as a Technical Program Committee Member for the International Solid-State Circuits Conference, the Custom Integrated Circuits Conference, and the VLSI Circuits Symposium. He is also the Editor-in-Chief of the IEEE Journal of Solid-State Circuits.