Start date: 07 December 2020
Duration: 2 hour class, 2pm - 4pm, on 5 days, Monday 7th Dec to Friday 11th Dec 2020
Location: Online course
Cost: Members €250 pp; Non-members €375 pp
Course code: N/A
This course held in Dec 2020 could be run again if there werer sufficient interest. Please contact the Skillnet to request it being re-run again. It comprises 5 days of 2 hour lectures / day from Prof. Hanumolu focusing on Signaling in Wireline SERDES Transceivers design, in which he is an accomplished researcher. A second course focusing on Wireline SERDES Clocking was held in Jan 2021.
- Latest signaling techniques in high speed serial interface design
Who is the course for?
Experienced analog IC designers, who wish to deepen their knowledge about signaling in high speed serial interface design and learn from a world class expert on this topic.
2 hour online class each day, 2pm to 4pm, on Monday to Friday 7th to 11th Dec. This is Part I of a two courses on this topic focused on Signaling. Part II focused on Clocking will be held in January:
3. Performance analysis tools
1. Current-mode drivers
2. Voltage-mode drivers
FIR equalizers/Feed-forward equalizers
2. Tx-side FFE
3. Rx-side FFE
3. Equalizer adaptation
Prof. Pavan Hanumolu (Member, IEEE) is a Professor with the Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Champaign, IL, USA. His research interests are in energy-efficient integrated circuit implementation of analog and digital signal processing, sensor interfaces, wireline communication systems, and power conversion. Prof. Hanumolu has served as a Technical Program Committee Member for the International Solid-State Circuits Conference, the Custom Integrated Circuits Conference, and the VLSI Circuits Symposium. He is also the Editor-in-Chief of the IEEE Journal of Solid-State Circuits.